Slew-enhanced operational amplifiers have input stages that operate in class-AB mode such that the available slew currents are independent of and not limited by quiescent currents. FIG. 1 is a simplified schematic of an exemplary slew-enhanced input stage 102 combined with a classic rail-to-rail output stage 104. The input stage 102 includes transistors Q101-Q108, current mirrors 126 and 128, a number of current sources, and a resistor Rgm. The current mirror 126 is made up of pnp transistors. The current mirror 128 is made up of npn transistors. The output stage 104 includes transistors Q109-Q118, compensation capacitors CCP and CCN, and a current source. While the currents produced by the current sources in a FIG. 1 and the remaining FIGS. are shown as producing quiescent current Iq, other current values are also possible. Additionally, all the various current sources in a same FIG. need not produce the same current.
The input stage 102 is a typical class-AB type, where the differential current through the resistor Rgm can be much larger than quiescent current Iq. One of each pair of differential currents sent toward ground and Vs are returned through current mirrors 126 and 128 and merged with the other current and made single-ended by the output stage 104. These combined currents represent the difference of the +input (+IN) to −input (−IN) and are sent to the bases of the output transistors Q117 and Q118. The collectors of the output transistors Q117 and Q118 join to form the output terminal. The eight transistors Q109-Q116 connected to the bases of the output transistors Q117 and Q118 are for biasing the output transistors Q117 and Q118 to a known quiescent current and controlling the crossover between the output transistors Q117 and Q118. All this circuitry is well-known.
The circuit of FIG. 1 has several drawbacks. One is that the open-loop gain diminishes badly with output loading. When an output transistor Q117 and/or Q118 drives output current, it will require base current which is ultimately derived from an error voltage across the resistor Rgm. Ultimately, this will limit gain to around 30 with a 150% load and typical values for resistor Rgm. Because npn and pnp betas are generally unequal, there will also be nonlinearity between + and − output signals. There needs to be more beta between the input transconductance (gm) and the output.
Another drawback of the circuit of FIG. 1 is that the input signals cannot linearly go less than about a volt above the low voltage rail (e.g., ground or −Vs). Here, the low voltage rail will be presumed to be ground. In single supply circuits, complying with ground-level signals is virtuous.